1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a shallow trench isolation structure and method for forming the same in which protective sidewall spacers are strategically formed upon the exposed sidewall surfaces of the shallow trench proximal to the upper surface of the semiconductor surface.
2. Description of Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Isolation structures are needed to electrically isolate one device from another. Isolation structures define the field regions of the semiconductor substrate while the device areas define the active regions (or mesa regions). The devices are interconnected with metal conductors disposed across an interlevel dielectric arranged above the devices and the semiconductor substrate. Low resistance contacts extending through the interlevel dielectric from the conductors to the active regions serve to couple these two levels of the integrated circuit together.
A popular isolation technology used in integrated circuits involves the process of locally oxidizing silicon. Local oxidation of silicon, i.e., "LOCOS", involves oxidizing those field regions of the semiconductor substrate interposed between active regions. The silicon dioxide ("oxide") grown in field regions is termed "field oxide". Field oxide is typically grown during the initial stages of integrated circuit fabrication before source and drain implants are forwarded into active regions. By growing a relatively thick field oxide in the field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends entirely across the field region and can unacceptably laterally encroach into the device active region as a bird's-beak structure. Second, the pre-implanted channel-stop dopant often redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active region periphery, causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as "shallow trench isolation". Despite advances made to decrease bird's-beak encroachment, channel-stop migration, and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron technologies. The shallow trench isolation process is better suited for isolating densely spaced active devices having field regions less than, e.g., 3.0-5.0 microns in the lateral dimension. The trench isolation process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then filling the shallow trench with a deposited dielectric (referred to henceforth as "trench dielectric"). Some trench isolation processes include an interim step of growing oxide on trench walls prior to the trench being filled. After the trench is filled, it is then planarized to complete the isolation structure. The trench process, inter alia, eliminates bird's-beak and channel-stop dopant redistribution problems.
Chemical-mechanical polishing ("CMP") is a technique currently used in the industry to planarize dielectric layers and, more specifically, trench dielectrics. CMP combines a mechanical polishing pad with a chemical slurry to remove dielectric material. CMP is typically a "dirty" procedure in that polishing-slurry particles and other residues accumulate upon the surface of the semiconductor topography during CMP. These contaminants must be cleaned from the semiconductor topography after the CMP process is complete. An RCA cleaning method may be used to clean the upper surface of the semiconductor topography. RCA cleaning first involves removal of organic film contamination followed by the application of an inorganic ion and heavy metal cleaning step. The RCA cleaning method acts upon and slightly removes the trench dielectric upper surface to a greater degree than adjacent silicon.
Subsequent processing steps may eventually lead to the upper surface of the trench dielectric being significantly displaced below the surface of the semiconductor substrate. In particular, the trench dielectric may undergo etching during the formation of dielectric spacers laterally adjacent to opposed sidewall surfaces of a polycrystalline silicon ("polysilicon") gate conductor arranged upon the substrate laterally spaced from the trench dielectric. The dielectric spacers are typically formed using an anisotropic etch in which ion bombardment occurs more frequently upon horizontal surfaces than vertical surfaces of a dielectric material deposited across the gate conductor, the substrate, and the trench dielectric. The duration of the etch process is terminated when the dielectric material has been removed from all surfaces except the sidewall surfaces of the gate conductor. Unfortunately, in order to achieve the desired lateral thickness of the dielectric spacers, the exposed horizontal surface of the trench dielectric must undergo substantial ion ablation before the etch process can be terminated. Furthermore, the surface of the trench dielectric may also be lowered as a result of exposure to subsequent cleaning processes using, e.g., an HF based solution.
Lowering the upper surface of the trench dielectric below the upper surface of the semiconductor substrate can, unfortunately, present many problems. After dopants have been implanted into source/drain junctions of the active regions between the gate conductor and adjacent trench dielectric structures, highly conductive ohmic contacts must be formed between the source/drain junctions and overlying interconnect. A self-aligned silicide ("salicide") is typically formed at the juncture between the ohmic contacts and the junctions. Salicide formation involves deposition of a refractory metal across the semiconductor topography followed by heating the refractory metal so as to cause the metal to react with underlying silicon. The resulting salicide is thus exclusively present upon regions of the semiconductor topography heavily concentrated with silicon, e.g., the source/drain junctions. If a trench dielectric is recessed below adjacent source/drain junctions such that sidewalls of the silicon-based substrate are exposed, silicide formation may occur upon those exposed sidewalls. Consequently, the relatively low resistivity silicide can undesirably form a conductive pathway between the source/drain junctions and the oppositely doped underlying semiconductor substrate. Thus, when attempting to produce a drive current between the source and drain junctions by applying voltages to the gate and to one of the transistors, the majority charge carriers may be drawn away from rather than toward the channel region of the transistor. As a result, current flow from the source to the drain may be minimal, leading to inoperability of the transistor.
It would therefore be beneficial to form a trench dielectric and adjacent transistors in a manner that inhibits bridging between source/drain junctions and an underlying semiconductor substrate. The presence of silicide upon the sidewalls of an isolation trench proximate the surfaces of adjacent source/drain junctions can create a conductive path between the junctions and the bulk substrate, leading to inoperability of the transistor employing the junction. It is therefore necessary to prevent silicide formation upon the sidewalls of an isolation trench in close proximity to the surfaces of adjacent active regions while forming silicide upon the upper surfaces of source/drain transistor junctions.